The present invention relates generally to memory systems and in particular, to virtual ground flash EPROM memory array systems and methods to eliminate the effects of charge sharing leakage currents to adjacent bits and loss in transient sense current during memory cell current read operations, resulting in substantially improved signal margins.
Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells are typically comprised of a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell MOS device. In an erase or program operation the voltages are applied so as to cause a charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 1 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
FIG. 1 illustrates a typical NOR configuration 100, wherein the control gate 110 is connected to a wordline (e.g., WL0 thru WL3) associated with a row of such cells 120 to form sectors of such cells. In addition, the drain regions 130 of the cells are connected together by a conductive bitline (e.g., BL0 thru BL3). The channel of the cell conducts current between the source 140 and the drain 130 in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal 130 of the transistors 120 within a single column is connected to the same bitline. In addition, each flash cell 120 associated with a given bit line has its stacked gate terminal 110 coupled to a different wordline (e.g., WL1 thru WL4), while all the flash cells in the array have their source terminals 140 coupled to a common source terminal (CS). In operation, individual flash cells 120 are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed, for example, by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called xe2x80x9cFowler-Nordheimxe2x80x9d tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
For a read operation, a certain voltage bias is applied across the drain to source of the cell transistor. The drain of the cell is the bitline, which may be connected to the drains of other cells in a byte or word group. The voltage at the drain in conventional stacked gate memory cells is typically provided at between 1.0 and 1.5 volts in a read operation. A voltage is then applied to the gate (e.g., the wordline) of the memory cell transistor in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed threshold voltage (VT) and an unprogrammed threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell.
In addition to the NOR configuration, some prior art flash memories also use a xe2x80x9cvirtual groundxe2x80x9d architecture, as shown in FIG. 2. A typical virtual ground architecture 200 comprises rows 240 of flash cells 210 with its stacked gate terminal 215 coupled to an associated wordline (e.g., WL0 thru WLn) 240, and columns (260, 270, 280, 290) of flash cell pairs (210 and 230) with a drain 235 of one transistor 230 coupled to an associated bitline (e.g., BL0 thru BLm) and the source 220 of the adjacent transistor 210 coupled to the same bitline 270. In addition, each single row of flash cells (e.g., 210 and 230) associated with a wordline 240 is connected in series, with the source 220 of one cell 210 coupled to the drain 235 of an adjacent cell 230, wherein each drain terminal of the transistors within a single column is connected to the same bitline.
An individual flash cell is selected via the wordline and a pair of bitlines bounding the associated cell. For example, in reading the flash cell 210, a conduction path would be established when a positive voltage is applied to the bitline (BL0) 260 coupled to the drain of flash cell 210, and the source 220 which is coupled to the bitline (BL1) 270, is selectively coupled to ground (VSS). Thus, a virtual ground is formed by selectively switching to ground the bitline associated with the source terminal of only those selected flash cells which are to be programmed or read.
FIG. 3 illustrates that just as with the NOR configuration, the typical prior art virtual ground flash memory array sector 300 comprises both row decode logic circuits 320 for selecting one or more wordlines 325, and column decode logic circuits 330 for selecting one or more bitlines 335. The array sector of flash cells 310, for example, comprises 512 rows and 64 columns of memory cells, which are associated with 512 wordlines and 64 bitlines, respectively.
As shown in FIG. 4, a conventional prior art full array 350, may contain 16 such sectors (360 and 370) with associated wordline and bitline decode logic.
A typical prior art flash memory circuit configuration is shown in FIG. 5. The prior art virtual ground flash memory circuit 400, comprises both row decode logic circuits 420 for selecting one or more wordlines 435, and column decode logic circuits 450 for selecting one or more bitlines 445. The array of flash cells 440, also comprises one or more sectors (e.g., 512 rows and 64 columns) of memory cells, which are associated with an equivalent number of wordlines and bitlines. Alternately, bitlines in some virtual ground architecture implementations of column decode logic circuits are decoded in pairs, to select two or more bitlines at a time (e.g., the bitlines bordering a cell to be read).
In addition, various methods of sensing the logical state of the memory cell may be employed. Two of these methods will be discussed, they are a drain-side sensing scheme, and a source-side sensing scheme, respectively. Simply, the difference in these two sensing schemes is the particular side of the cell in which the associated bitline sensing circuitry resides. For example, in the drain-side sensing scheme the sensing circuitry is coupled to the bitline associated with the drain terminal of the cell to be sensed, while in the source-side sensing scheme the sensing circuitry is coupled to the bitline associated with the source terminal of the cell to be sensed. Either the drain-side or the source-side sensing circuits may also use, for example, a series current, a current mirror, or any other type of sensing configuration to the associated bitline. Initially the drain-side sensing will be discussed.
FIG. 5, for example, comprises drain-side sensing circuitry to read the flash cells of the prior art virtual ground circuit 400, which contains a Global precharge circuit 460 which precharges all the bitlines of one or more sectors of the array with the same positive voltage VD (e.g., about 1.2 volts) 445, as is used to sense the flash cell current via a cascode current-to-voltage preamplifier circuit 470. The cascode preamplifier circuit 470 supplies the positive voltage VD generated from the VCC 415 to a bitline on the drain side of the selected flash cell within the array 440, while the source side of the selected cell is coupled thru another bitline to the ground 480 via the virtual ground switch circuitry 490 to generate a core cell sense current ICORE 475. The cascode preamplifier circuit 470, converts the core cell sense current ICORE 475 to a core cell sense voltage VCORE 477 for use in a sense amplifier 476. The cascode preamplifier 470 also generates a reference current IREF and converts this to a reference voltage VREF 478, which is compared to VCORE 477 in the sense amplifier 476.
During reading, this sense voltage VCORE 477 associated with the flash cell sense current ICORE 475, is compared to the reference voltage VREF 477 in the sense amplifier 476 to produce a core cell verification indication 479 that the correct flash cell logical state is stored at the desired location.
FIG. 6 shows a method 500 and four basic steps (510, 520, 530, 540) which are employed to read conventionally a selected flash cell in the prior art virtual ground circuit of FIG. 5. Initially, in a step 510 which begins at time t0, all bitlines (BLO thru BLM) are first precharged to the same positive voltage VD (e.g., about 1.2 volts) as is used to sense the flash cell current. By a time t1 520, the bitlines are assumed to be precharged to a positive voltage VD. The global precharge circuit voltage VD, is then disconnected from all the bitlines at time t1 520, and the bitlines are allowed to float without an applied voltage. At time t2 530, a core cell 535 is selected with a bitline BLX 536 at the drain side of the cell, and with an adjacent bitline BLX+1 545 at the source side of the cell; and a wordline WLX coupled to the gate of the cell 535 to be sensed, while all other bitlines continue to float. Also during this step, the bitline BLX+1 545 is selectively coupled as a virtual ground to ground 547. At time t3 540, the flash cell 535 sensing operation 548 begins with the application of a wordline voltage at WLX, a bitline voltage VD at 536 to the drain, and a ground 547 to the source 545 of the selected flash cell 535.
Thus, an individual flash cell is selected via a wordline and a pair of bitlines bounding the associated cell. For example, in reading a flash cell of the sector of FIG. 6, a conduction path is established when a positive voltage VD is applied to one of the bitlines (e.g., BLX) 536 coupled to the drain of a flash cell, the source of the flash cell is coupled to an adjacent bitline (e.g., BLX+1) 545, which is selectively coupled to ground (VSS) 547, and an appropriate wordline (e.g., WLX) voltage is applied to the gate of the selected cell.
With a current established in the selected core cell, the core cell sense current 548 is converted to a cell sense voltage VCORE within the cascode current-to-voltage preamplifier circuit along with a reference cell voltage VREF which is passed to a sense amplifier (e.g., 476 of FIG. 5) to produce a core cell verification indication (e.g., 479 of FIG. 5) of the correct logical state of the flash core cell.
A drawback of the conventional method is best seen as in the global bitline voltage versus time plot 550 of prior art FIG. 7, and the core cell Sense current versus time plot 570 of prior art FIG. 8. As the global precharge of all the bitlines begins at time t0 555 in FIG. 7, the voltage on all the bitlines rapidly charges along line segment 560 toward the applied positive voltage VD (e.g., about 1.2 volts) 562. VD is briefly maintained on all the bitlines until time t1 556 at which point VD is disconnected from all the bitlines. After the precharge time to 555, and before the core cell select time t2 557, the voltage VD, which was applied globally to all the bitlines of one or more sectors, is allowed to float, and therefore discharges along the exemplary curve segment 563 to a lower voltage due to the leakage of the cells coupled to the selected wordline. The amount of time that this positive voltage VD will remain on the bitlines after VD is disconnected, is an RC function of the combined distributed capacitance of all the cells on the wordline, and the total leakage of all the individual cell leakages along each bitline. The source of this cell leakage current is a result of the sharing of the charge between all the associated cells (called charge sharing), and the material properties of the semiconductor structures.
Also, since all the cells associated along a wordline have their drains and sources coupled in series, these cells have a combined leakage path through the drain side of the cell being sensed. If a cell was selected, for example, at the end of the wordline, there could be as many as 64 cells combined leakage seen at the drain side of the cell whose current is being sensed.
At time t2 557, the bitlines bounding the cell to be sensed are selected along with the associated wordline. Upon selection, the flash core cell current ICORE is sensed by the cascode circuit and illustrated with line segment 580 of the cell sense current versus time plot of FIG. 8. The core cell current, however, is also being added to the total leakage current exhibited by all the cells coupled on the selected wordline. In the example 570, the total sensed current ILEAKAGE+ICORE (580) may be greater than the low core cell current ICORE, which should be read as a logical xe2x80x9c1xe2x80x9d. With a typical cell sense current set at, for example, about 100 uA (590), for the sense of a logical xe2x80x9c0xe2x80x9d state, the conventional cascode and sense amplifier circuitry would instead, incorrectly indicate a logical xe2x80x9c0xe2x80x9d state at 585 at time t3 558, as a result of the combined core cell current and leakage current.
Referring back to FIG. 7, the bitline voltage has continued to discharge and drop along line segment 563 until at time t3 558 the selected cell sense current is made. At a sense voltage 568 associated with this cell sense current 590, and point 565 on line segment 563, a voltage drop has been established between the drain of the cell being sensed and the drain of the adjacent drain side cell. The voltage drop induced across the cells increases the leakage currents in those cells, and increases the resultant error in the sense current readings (read signal margins).
Additionally, the voltage drop induced across the cells by the discharging voltage which was applied globally to the bitlines, has a dynamic or variable characteristic as shown in the curves 550 and 570. The dynamic characteristics of the leakage currents makes the cell sense current read operation inconsistent, and degrades the read signal margins. Such sense current variations degrades the ability in the read mode circuitry to discriminate accurately whether or not a cell is programmed.
Although the drain-side sensing scheme has been discussed here, it should be realized that source-side sensing schemes also are subject to leakage to adjacent cells and therefore to errors in read operations in many similar ways. Drain-side sensing has precharge voltages applied directly to the cells adjacent to the sensed cell, which float or discharge to another level thereby causing a differential voltage and a ready leakage path. Source-side sensing also has cells adjacent to the sensed cell which may be floating at some voltage which remains on the cell from a previous memory operation (e.g., read, erase, program) which was performed. For either sensing scheme, therefore, the voltage drop across the adjacent cell at the sensed side of the read cell, represents a path for leakage current and a read sense error.
Accordingly, there is a need for a stable means of eliminating the effects of charge sharing leakage currents to adjacent bits and loss in transient sense current during memory cell current read operations, resulting in substantially improved signal margins in a virtual ground flash EPROM memory array system.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Its primary purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention is directed to a system and method of eliminating the effects of charge sharing leakage currents to adjacent flash cells and loss of sense current during memory cell current read operations, which result in substantially reduced read errors in a virtual ground flash memory array system.
The present invention provides bitline precharge and hold circuitry, as well as a combination of selective bitline decode circuitry and methodologies by which a precharge voltage may be applied to a specific bitline adjacent to a sensed memory cell during memory read operations, wherein applying a precharge voltage VSS (e.g., about 0 volts, or ground) to the bitline at the source terminal (source side bitline) of the cell adjacent to the source side of the cell being sensed, reduces or cancels the leakage current which is conventionally associated with the adjacent cell.
Leakage current variations in the memory cells are typically reflected in the read sense current output of the memory cell sense amplifier circuit which causes incorrect indications of the memory cell logical states. These reading errors are referred to as xe2x80x9cread marginsxe2x80x9d. By applying the substantially same voltage to the adjacent cell source bitline, as is applied to the sensed cell source bitline, a voltage drop across the adjacent cell is substantially eliminated and therefore variations in the read sense current output are avoided. The current output is applied to a source side sensing circuit which produces an associated read sense voltage which is passed to a sense amplifier to produce the memory cell logical state indication. With the current variations due to adjacent cell leakage eliminated, a more consistent memory cell reading is insured. These features are provided by the source-side sensing scheme of the present invention.
A feature of the sensing scheme of the present invention is that fewer bitlines need be precharged, (e.g., only two bitlines are precharged), in contrast to all the bitlines of a sector or all the bitlines of an entire array being charged with conventional sensing schemes.
Another feature of the sensing scheme of the present invention is that a more stable output indication is possible than with conventional schemes by eliminating the dynamic characteristics due to leakage between adjacent cells and variations in the resultant cell sense current, and read signal margins are improved. This feature is particularly advantageous in multibit memory devices, where higher signal margins are needed to differentiate between the threshold distribution regions of each bit.
Yet another feature of the sensing scheme of the present invention is that by eliminating the effects of leakage to adjacent cells, leakage considerations as a part of manufacturing are reduced.
An advantage of the present invention over conventional sensing schemes, is the elimination of the dynamic discharge characteristic of the bitlines and array cells. In addition, the present invention also eliminates the variations of the cell current reading due to the timing of the reading after the cell sense or precharge voltage is disconnected. Thus, timing of the reading does not affect the actual reading.
Thus a memory system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations, which is substantially independent of charge sharing leakage currents to adjacent cells.
The aspects of the invention find application in devices which include virtual ground memory cells architectures, where memory cell leakages may be higher, and in association with multibit memory devices employed in higher signal margin applications.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.